Subranging technique using superconducting technology

ABSTRACT

Subranging techniques using “digital SQUIDs” are used to design systems with large dynamic range, high resolution and large bandwidth. Analog-to-digital converters (ADCs) embodying the invention include a first SQUID based “coarse” resolution circuit and a second SQUID based “fine” resolution circuit to convert an analog input signal into “coarse” and “fine” digital signals for subsequent processing. In one embodiment, an ADC includes circuitry for supplying an analog input signal to an input coil having at least a first inductive section and a second inductive section. A first superconducting quantum interference device (SQUID) is coupled to the first inductive section and a second SQUID is coupled to the second inductive section. The first SQUID is designed to produce “coarse” (large amplitude, low resolution) output signals and the second SQUID is designed to produce “fine” (low amplitude, high resolution) output signals in response to the analog input signals. The output signals of the first SQUID are coupled to a first comparator having an output for producing a first quantized output signal which is coupled back to the input coil. The output signals of the second SQUID are coupled to a second comparator having an output for producing a second quantized output signal which is also coupled back to the input coil. The outputs of the two comparators may then be further processed for producing a digital version of an analog input signal.

BACKGROUND OF THE INVENTION

[0001] This application claims the benefit of U.S. ProvisionalApplication Serial No. 60/232931 filed Sep. 9, 2000.

[0002] This invention was made with government support under contractNo. DE-FG02-98ER82799 from the Department Of Energy. The government hascertain rights in this invention.

[0003] Precise measurement of current is necessary in many applications.It is desirable to develop a high-precision, non-interceptive current(or flux) measuring scheme based on a digital SQUID (SuperconductingQUantum Interference Device) technology. The advantage of using SQUIDs,in general, and digital SQUID, in particular, is that this technologynot only improves the dynamic range of measurement systems, but alsoreduces the cost and complexity of supporting, peripheral electronics.Another desirable feature is that the digital nature of the outputslends itself to digital signal processing, naturally.

[0004] The following examples illustrate some applications in a nuclearfacility accelerator facility where high resolution over a wide range ofsignal amplitude is desirable.

[0005] 1) Beam Current Monitor (BCM)

[0006] The average circulating beam current must be measured to a veryhigh precision (10⁻⁴-10⁻⁶). This measurement can provide importantinformation about particle losses in a beam. Even small deviations inthe average beam current must be diagnosed to ensure stability of thebeam. Depending on the particulars of an accelerator, the maximumaverage beam current can range from 100 μA to 100 mA. Therefore, acurrent resolution of about 10 nA is needed.

[0007] 2) Beam-in-Gap Monitor (BIG)

[0008] The measurement of gap current, which is 10⁴-10⁵ times smallerthan the peak bunch current, is another demanding application. In theSNS (Spallation Neutron Source) ring, the bunch currents can be as highas 100 A. However, gap currents in the mA range must be measuredaccurately to determine the fraction of the beam outside the bunch.Since the gap duration is 250-300 ns, the measurement bandwidth must beat least several MHz. This is an extremely challenging task in terms ofboth dynamic range (10⁵) and slew rate of the measurement instrument.

[0009] 3) Beam Polarization Measurement

[0010] Direct measurement of beam polarization can be made if themagnetic flux produced by the aligned dipole moments in a polarized beamcan be measured. This is difficult because the magnetic fields producedby the charged particle are 10¹⁰-10¹⁵ times larger. An extremely highresolution measurement instrument is needed to measure such a smallsignal in the presence of an overwhelming background. By careful designof the pick-up coil, the background signal can be reduced to about 10⁸times the polarization signal. Still, detecting this signal will requireabout 27 bits of resolution.

SUMMARY OF THE INVENTION

[0011] Applicant's invention is directed to a subranging architectureusing digital SQUID (Superconducting QUantum Interference Device)technology to design systems with larger dynamic range, higherresolution and larger bandwidth than existing systems. Systems embodyingthe invention may be used to manufacture (current or magnetic flux)measuring instruments useful in a diverse range of applicationsrequiring high resolution and the sensing of signals over a wide rangeof signal amplitude.

[0012] An analog-to-digital converter (ADC) embodying the inventionincludes circuitry for supplying an analog input signal to an input coilhaving at least a first inductive section and a second inductivesection. A first superconducting quantum interference device (SQUID) iscoupled to the first inductive section and a second SQUID is coupled tothe second inductive section. The first SQUID is designed to produce“coarse” (large amplitude, low resolution) output signals and the secondSQUID is designed to produce “fine” (low amplitude, high resolution)output signals in response to the analog input signals. The outputsignals of the first SQUID are coupled to a first comparator having anoutput for producing a first quantized output signal which is coupledback to the input coil. The output signals of the second SQUID arecoupled to a second comparator having an output for producing a secondquantized output signal which is also coupled back to the input coil.

[0013] In one embodiment of the invention first and second clock signalsare respectively applied to the first and second comparators forenabling one of them at a time. In certain embodiments, the first andsecond inductive sections are connected in series. Typically, theinductance of the second inductive section is greater than theinductance of the first inductive section for causing the first SQUIDand the first comparator to produce a “coarse” output and the secondSQUID and the second comparator to produce a “fine” output.

[0014] In an embodiment of the invention each one of the first andsecond comparators is a superconducting comparator; with each one of thefirst and second comparators being responsive to an output signal of itscorresponding SQUID and to a clock signal for producing first and secondcomparator complementary output signals. The first output signal of eachcomparator is coupled to a first write gate and the second output signalof each comparator is coupled to a second write gate. The first writegate produces a comparator output signal of one binary value and thesecond write gate produces a comparator output signal of a second binaryvalue, with the output signals of the first and second comparators beingfed back to the input coil and to processing circuitry.

[0015] In a subranging superconducting ADC embodying the invention eachone of the first and second comparators includes a digital output, withthe digital output of the first comparator defining the more significantbits and the digital output of the second comparator defining the lessersignificant bits of the digitally converted signal.

[0016] The digital output of each comparator may be coupled to anup-down counter, with each up-down counter having an output coupled toan accumulator whose output is coupled to a processor for processing thedata digitally. The processor may include a digital filter and dataacquisition and software for analyzing the data.

[0017] A subranging superconducting ADC embodying the invention may alsoinclude a first circuit arrangement for producing “coarse” (highamplitude, low resolution) output signals and a second circuitarrangement for producing “fine” (low amplitude, high resolution) outputsignals. The first circuit arrangement includes circuitry for supplyingan analog input signal to a first inductor for inductively coupling theanalog input signal to a first SQUID based circuit. An output of thefirst SQUID based circuit is coupled to a first digital filter forproducing a “coarse” digital signal. The second circuit arrangementincludes circuitry for subtracting an output of the first SQUID basedcircuit from the analog input signal and applying the resultant analogsignal to a second SQUID based circuit. An output of the second SQUIDbased circuit is supplied to a second digital filter for producing a“fine” digital signal.

[0018] In one embodiment, the circuitry for subtracting an output of thefirst SQUID based circuit from the analog input signal includes ananalog delay line for coupling the analog input signal to a secondinductor and a digital variable delay network having an input connectedto the output of the first SQUID based circuit and having an outputconnected to the input of a digital-to-analog converter (DAC) with theoutput of the DAC being connected to a third inductor and supplying asignal thereto tending to cause the output of the first SQUID basedcircuit to be subtracted from the analog input signal developed acrossthe second inductor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, like reference characters denotelike components; and

[0020]FIG. 1(a) is a schematic diagram of a prior art analog SQUID withfeedback;

[0021]FIG. 1(b) is a schematic diagram of a prior art digital SQUIDusing a 1-bit delta modulator scheme;

[0022]FIG. 2 is a schematic diagram of a prior art feedback circuit tolinearize the transfer characteristic of an analog SQUID;

[0023]FIG. 3 is a semi-schematic semi-block diagram of a two-channelsubranging circuit embodying the invention;

[0024]FIG. 3A is a semi-schematic semi-block diagram of anothertwo-channel subranging circuit embodying the invention;

[0025]FIG. 4 is a schematic diagram of a “coarse” resolution channeluseable in the circuit of FIG. 3 showing the various transformerconfigurations;

[0026]FIG. 4A is semi-schematic, semi-block diagram of a comparatorcircuit with two thresholds useable in circuits embodying the invention;

[0027]FIG. 5 is an equivalent circuit (the WRSpice model) of the“coarse” channel circuit of FIG. 4;

[0028]FIG. 6 is a top view of a layout showing some components of thecoarse resolution channel.

[0029]FIG. 7 is a schematic diagram of a fine resolution channel useablein the circuit of FIG. 3 (or FIG. 3A) showing various transformerconfigurations;

[0030]FIG. 8 is an equivalent circuit (the WRSpice model) of the fineresolution channel of FIG. 7;

[0031]FIG. 9 is a top view of a layout showing some of the components ofthe fine resolution channel;

[0032]FIGS. 10 and 11 illustrate the output produced by circuitsembodying the invention in response to a linearly increasing inputsignal;

[0033]FIG. 12 is a block diagram of a modular precision currentmeasurement instrument based on the digital SQUID technology;

[0034]FIG. 13 is semi-schematic/semi-block block diagram of atwo-channel subranging circuit embodying the invention and of circuitryfor processing the outputs of the two channels;

[0035]FIG. 14 is a micro-photograph of a high resolutionanalog-to-digital converter (ADC) circuit suitable for use with digitalSQUIDs embodying the invention;

[0036]FIG. 15 is a micro-photograph highlighting the placement of theinductors in the layout of a digital SQUID embodying the invention;

[0037]FIG. 16 is a schematic diagram of a two clock comparator which maybe used in circuits embodying the invention;

[0038]FIG. 17 is an illustrative drawings of two possible schemes forcombining the outputs of the fine and coarse resolution channels;

[0039]FIG. 18 is a block diagram of a subranging analog-to-digitalconverter (ADC) in accordance with the invention; and

[0040]FIG. 19 is a more detailed diagram of the signal subtractionscheme shown in the circuit of FIG. 18.

DETAILED DESCRIPTION OF THE INVENTION

[0041] In the discussion to follow, it should be understood that“Sensitivity” of a measuring device is the smallest signal that can bedetected in the presence of noise. SQUIDs are very sensitive measurementdevices for magnetic flux. Resolution is a property of a digital deviceand refers to the smallest discrete level. This is also referred to asthe least significant bit (LSB). The fundamental flux resolution of aSQUID-based device is a single flux quantum (F0 or Φ0), but theresolution of an ADC can be improved further through digital filteringif the sampling frequency is higher than the twice the signal bandwidth(Table 1).

[0042] Measurement of the characteristics of a signal current can bemade by measuring the magnetic flux it produces in a pick-up loop (e.g.,10 in FIG. 1(a)). A very precise measurement of magnetic flux (Φ) can beperformed with a SQUID (Superconducting Quantum Interference Device).

[0043] The magnetic flux in a SQUID (e.g., 12 in FIG. 1(a))causes avoltage (V) to appear across it. [Note that in FIGS. 1(a) and 1(b) andin all the other drawings, the symbol “X” in a drawing is used tospecifically identify the presence of a Josephson junction (J or JJ).] ASQUID is a non-linear device with a periodic transfer characteristic(V-Φ curve). To increase the dynamic range of a SQUID amplifier, thetransfer function must be linearized by using feedback. As shown in FIG.1(a) a common method of achieving this is to magnetically couple a pickup coil 10 with a feedback coil, carrying a current proportional to V,to the SQUID. This feedback can be done either using on-chip circuitryor through external, room temperature electronics.

[0044] The SQUID 12 is biased in the center of the linear region of itsV-Φ curve. As the externally applied flux (Φ) increases, the voltage (V)across the SQUID also increases, resulting in a proportional increase inthe feedback current. The feedback current produces magnetic flux, equaland opposite to the input flux, in the SQUID. By measuring the feedbackcurrent, the externally applied flux and the current producing that fluxcan be calculated. This is a null detection scheme.

[0045]FIG. 2 shows a common measurement configuration, which may bereferred to as a flux-locked loop, where an ac signal from an oscillatoris added to the feedback current to facilitate a narrow-band lock-inmeasurement. Usually the transformer turns ratio between the SQUID andthe signal/feedback coil is high, of the order of 100. Therefore, smallerrors in measurement in the SQUID are manifested as large ones in thecurrent through the feedback network. The output is the feedback currentrequired to produce the same amount of flux in the SQUID induced by theinput (signal) coil.

[0046] The major disadvantages of this method are:

[0047] 1) Limited dynamic range dependent on current-carrying capacityin the feedback coil,

[0048] 2) Analog output that may require analog-to-digital conversionfor further signal processing,

[0049] 3) Expensive peripheral electronics, and

[0050] 4) Large errors.

[0051] Digitizing the SQUID output and providing a digital feedback isdesirable to improve the -dynamic range and produce digital outputs.This may be done as shown in FIG. 1(b). There are many methods ofimplementing a digital SQUID; where a “digital SQUID” as used hereinincludes an analog SQUID whose output is coupled to a circuit, such as acomparator, to produce a digital output signal which is fed back to theinput of the analog SQUID. However, a desirable and relatively simplescheme may be used as shown in FIG. 1(b) and which is referred to as a1-bit delta modulator 18. In this scheme, the analog dc SQUID 12 ismagnetically coupled to a clocked comparator circuit. The feedback is inthe form of single flux quanta (SFQ) injected directly into the pick-upcoil loop 10.

[0052] The operation of the 1-bit delta modulator is briefly outlined asfollows: In the absence of an external flux, the comparator 18 switchesto a voltage state and causes write gate 1 to induce a single fluxquantum (Φ₀=h/2e=2.07×10⁻¹⁵ Wb) into the pick-up loop. This flux issensed by the analog SQUID and is applied back to the comparator. In thefollowing clock cycle, this magnetic field keeps the comparator fromswitching and causes the write gate 2 to switch and, hence, it inducesan antifluxon (−Φ₀) in the loop annihilating the original fluxon. Aslong as there is no applied flux, this process of fluxon/antifluxoncreation/annihilation continues. This is the steady state operation ofthe 1-bit delta modulator circuit.

[0053] Depending on the polarity of the input flux (or current), thecomparator circuit injects either +Φ₀ or −Φ₀ directly into the inputcoil through one of the two write gates. For example, if the input fluxis positive, the comparator produces −Φ₀ into “write gate 2” when aclock pulse arrives. This causes partial cancellation of the flux in theinput coil. The process continues until the flux in the loop falls belowthe threshold of the comparator. Any change in the value of the inputflux is tracked in steps of Φ₀. As long as the flux does not change bymore than Φ₀ in a clock period—the slew rate limit—the SQUID outputfaithfully tracks the flux. The digital output of the comparator issynchronized with the clock. By counting the digital output, theexternally applied flux (or current) can be measured.

[0054] Since the feedback is quantized, so is the resolution of thedigital SQUID. The flux resolution is Φ₀ (2.07 fWb=2.07 nA·μH). Thecurrent resolution (ΔI) depends on the inductance (L₁) of the inputcoil. For an input inductance of the pickup coil of 1 μH, ΔI=Φ₀/L₁≈2 nA.Thus, the resolution can be changed by varying the input inductance. Incircuits embodying the invention this feature is used to produce digitalSQUIDs of “coarse” and “fine” resolutions.

[0055] In calculations of current resolution thus far, only the rawresolution was considered. For low-bandwidth and dc measurements, suchas average beam current monitoring, higher resolution can be obtained byexploiting over sampling.

[0056] If the clock frequency is higher than the Nyquist rate for agiven bandwidth, the resolution can be improved further by averaging theoutput. A digital filter can be employed to perform this averaging. Theresolution improves by a factor of {square root}{square root over (α)},where α is the over sampling ratio (OSR). If the input bandwidth is 100Hz, corresponding to a Nyquist frequency of 200 Hz, and the clockfrequency is 200 MHz, α=10⁶. In that case, the resolution can beimproved by a factor of 1000. For the example above, the currentresolution becomes 2 pA. While extremely high resolution is possible fora direct current (dc) measurement, the current resolution is ultimatelylimited by the noise in the SQUID. The digital SQUID technology, in thepresent implementation, is ideal for extremely high-resolutionmeasurement of slow signals. If high-resolution measurement of signalswith MHz bandwidths is desired, a more complex version of the circuitwith on-chip RSFQ digital filter can be used in conjunction with a clockfrequency in the GHz range.

[0057] The slew rate of the digital SQUID is proportional to the clockfrequency (f_(c)) and is equal to Φ₀×f_(c)/N where N is the transformerturns ratio between the input coil and the SQUID. In analog SQUID, slewrates of 10⁶ Φ₀/s are possible. To achieve the same slew rate in adigital SQUID with a 100-turn transformer, a clock frequency of 100 MHzis needed. The input current slew rate Φ₀×f_(c)/L₁) is 0.2 A/s for a 1μH input inductance. The sensitivity of a digital SQUID is the same asthe analog dc SQUID it uses, and is in the range of 10⁻⁵-10⁻⁶ Φ₀/{squareroot}Hz.

[0058] Another advantage of a digital SQUID is the digital nature of theoutput. The digital output helps simplify the processing electronicsconsiderably. It also enables more freedom in signal processing. Forexample, a programmable digital filter can be used to vary themeasurement bandwidth.

[0059] Table 1 shows a comparison of the different parameters of theanalog [e.g., FIG. 1(a)] and the digital [e.g., FIG. 1(b)] SQUID. Theunlimited dynamic range and high-resolution digital output are the twomajor advantages of the digital SQUID. These can be exploited toimplement a superior instrument for precise measurement of magnetic fluxand, therefore, other quantities like current, magnetic field andvoltage. TABLE 1 Comparison of analog and digital SQUID Parameter AnalogSQUID Digital SQUID Dynamic Range 10⁴-10⁵ Unlimited Limited by feedbackelectronics Slew Rate 10⁶ Φ₀/s Φ₀ × f_(c)/N = 10⁴-10⁷ Φ₀/s Limited byf_(c) = clock freq., feedback electronics N = turns ratio Sensitivity10⁻⁵-10⁻⁶ Φ₀/{square root}Hz 10⁻⁵-10⁻⁶ Φ₀/{square root}Hz Resolution Notapplicable Φ₀/{square root}α α = Oversampling ratio Room temperatureComplex and Simple and inexpensive electronics expensive ProgrammabilityNo Yes

Subranging Digital SQUID Architecture

[0060] While the dynamic range of each digital SQUID is unlimited, theslew rate is not. Note: The dynamic range is the ratio of the maximumsignal that can be measured to that of the minimum signal that can bemeasured. The slew rate is the time rate of change of signals.

[0061] To reduce the slew rate limitation, a subranging architecture ofthe type shown in FIG. 3 and which embodies the invention is used.Referring to FIG. 3, there is shown a pick-up coil (Lp) which representsthe element for sensing the current or magnetic field which is beingmeasured. The pick-up coil (Lp) is coupled to an input coil 31 which, inthis embodiment, is formed to have a first coil section (identified asL1) in series with a second coil section (identified as L2). Theinductor L1 is made to have fewer turns than L2 so the inductance of L1is less than the inductance of L2. The inductor Li is part of a “coarse”current resolution channel which is further detailed in FIGS. 4, 5 and6. The inductor L2 is part of a “fine” current resolution channel whichis further detailed in FIGS. 7, 8 and 9.

[0062] A significant aspect of the FIG. 3 embodiment is the use of thesame input coil 31 to provide input to the “coarse” and “fine” SQUIDbased circuits and to the operation of these two SQUID based circuitsfrom a common clock signal(s) to produce outputs which can besubsequently recombined to produce an output signal indicative of thevalue of the input signal sensed by the pick-up coil and coupled to theinput coil 31.

[0063] The subranging circuit of FIG. 3 includes two SQUIDs (SQ1, SQ2),coupled to the same input coil 31. SQUID SQ1 is coupled at its input toinductor L1 and is magnetically coupled at its output to a comparator101. SQUID SQ2 is coupled at its input (via a step down transformer L3)to inductor L2 and is magnetically coupled at its output to a comparator102. Comparators 101 and 102 are also SQUIDs (see detailed structureshown in FIGS. 5 and 8). Comparators 101 and 102 are clocked (clock A,clock B) and the outputs of the comparators are fed back to the inputcoil 31. The interconnection of SQUID SQ1 and comparator 101 defines the“coarse” resolution channel. The interconnection of SQUID SQ2 andcomparator 102 defines the “fine” resolution channel. The coarseresolution SQUID, SQ1, measures the current in larger steps leaving asmaller current, less than its step size (resolution), to be measured bythe fine resolution SQUID with smaller steps. In the circuit of FIG. 3,the two coarse and fine channels may be alternately clocked; i.e., firstone and then the other. Alternatively, the coarse channel can first beclocked consecutively and repeatedly until the steps are less than the“coarse” resolution. Then, the fine channel can be clocked until thesteps are less than the “fine” resolution. The digital outputs (DO1,DO2) from the two SQUIDs can then be combined off chip or on chip (SeeFIG. 13).

[0064] The input SQUIDs SQ1 and SQ2 are analog SQUIDs which are oftenreferred to as DC SQUIDs in the literature. These SQUIDs arecurrent-biased (I_(bias)>I_(c)) above their critical current, in theirvoltage state. The analog SQUID produces a voltage that is a function ofthe flux applied to it. By connecting the output of each input SQUID toa series resistor and a transformer (see R5, T102 in FIGS. 5 and R5,T102 b in FIG. 8) a magnetic flux proportional to the SQUID voltage isapplied to its associated and corresponding comparator SQUID. Note thatthe flux input to the analog input SQUID (SQ1 and SQ2) is appliedthrough a transformer, consisting of a secondary coil, which is theinductance of the SQUID loop and a primary coil, which is part of theinput circuitry, that may contain a pick-up coil and the feedbacknetwork. The flux coupled to each analog input SQUID (SQ1, SQ2) is thesum of the input flux and the feedback flux signals and always keptbelow Φ₀ for optimum operation.

[0065] In FIG. 3, the input coil 31 is split into two parts, L1 and L2connected in series. The top SQUID, SQ1, is coupled to L1, to providethe coarse resolution while the bottom SQUID, SQ2, is coupled to astep-down transformer, L3, which is coupled to L2 to provide fineresolution. The coarse resolution SQUID measures the current in largersteps leaving a smaller current, less than its step size (resolution),to be measured by the fine resolution SQUID with smaller steps. Itshould be appreciated, as shown in FIG. 18, that the input coil 31 canbe split into two separate parallel sections (i.e., non-seriesconnection) with each section providing a different degree ofresolution.

[0066] In one embodiment of the circuit of FIG. 3, L₁ was made 500 pHand L₂ was made 1 μH. The input of coarse SQUID, SQ1, is coupled to L₁which is the smaller (lower inductance) part of the input coil. Thedigital feedback from comparator 101 is injected directly into the inputcoil, tending to keep the flux in the input coil always below Φ₀. Thecurrent resolution of the coarse SQUID is ΔI_(coarse)=Φ₀/L₁. This allowsthe measurement of large currents using the coarse digital SQUID. Thefine resolution SQUID, SQ2, which may be like SQ1, is coupled to thelarger part (higher inductance) of the input coil, L₂, through the stepdown transformer, L3. The digital feedback from the fine resolutionSQUID, SQ2, obtained from comparator 102 is injected into the step-downtransformer coil, L3. The step-down transformer coil L3 provides goodsignal coupling while also providing an intermediate transformationbetween the small inductance L_(SQ) of SQ2 and the much largerinductance of L2.

[0067] The step down transformer consists of a “washer” and a “coil” inseries, where the term “washer” is as used in the art and refers to theshape of an almost ideal coupling element formed above or below a coil.The washer couples to L₂, and the coil couples to the fine resolutionSQUID, SQ2. The washer and the coil were designed to have the sameinductance L₃. This makes the design of this transformer challenging. Inone embodiment, L₃ was designed to be 500 pH. The resolution of the“fine” SQUID is ΔI_(fine)=Φ₀/L₂.

[0068] Assuming the inductor values to be L₁=500 pH, L₂=1 μH, L₃=500 pH,and L_(SQUID)=20 pH, calculations yield the coarse resolution to beΔI_(coarse)=Φ₀/L₁=4 μA and the fine resolution to be, ΔI_(fine)=Φ₀/L₂=2nA. The actual fine resolution may be more than 2 nA due to couplinglosses. These raw resolution numbers can be improved by averaging(integrating) by a factor of {square root}{square root over (α)}, whereα is the over sampling ratio (OSR).

[0069] This type of subranging measurement architecture is useful inmeasuring gap currents for a Beam-in-Gap (BIG) monitor in a SpallationNeutron Source (SNS), which are 10⁵-10⁶ times smaller than the bunchcurrent.

[0070] In one embodiment of the invention the coarse resolution SQUID,SQ1, is first used to cancel the flux in the pick-up loop until theamplitude of the input signal is below a “coarse” resolution step. Then,the fine resolution SQUID, SQ2, takes over when the flux in the pick-uploop is smaller than the resolution of the coarse SQUID. In FIG. 3, the“coarse” and “fine” channel comparators are clocked by two clock pulses(clock A and clock B) that are 180 degrees out of phase. That is,comparator 101, which is used for the “coarse” channel, is clocked by aclock signal, Clock A, and comparator 102, which is used for the “fine”channel, is clocked by a clock signal, Clock B; where clock A and clockB are 180 degrees out of phase relative to each other, but are both insynchronism with the clock signal 100 applied to the two-phase SFQ clockgenerating circuit 42. The advantage of using a two-phase clock is thatonly one of the two channels is read out for each clock pulse. The fineresolution SQUID never has to track large changes of input flux (orcurrent). The maximum current it has to measure is ΔI_(coarse). The timeresolution of the measurement is the clock period. Therefore, changes inthe input current occurring between successive clock pulses cannot bemeasured. Note that the clocking circuit may be modified as shown inFIG. 3A, which includes clock controller 300, which may be programmedto: a) repeatedly and consecutively clock the comparator of the coarsechannel and then the comparator of the coarse channel; or b) clock thetwo channels alternatively.

[0071] Thus, circuits embodying the invention include digital SQUIDs(SQ1 and its comparator, SQ2 and its comparator) with two differentcurrent resolutions coupled to a common pick-up coil. These types ofdigital SQUID circuits provide a wide dynamic range and high resolution,enabling the manufacture of versatile digital SQUID measuringinstruments. Circuits embodying the invention demonstrate thefeasibility of a subranging digital SQUID. The subranging architectureincludes a coarse resolution channel and a fine resolution channel usinga wide dynamic range and high-resolution digital SQUID. The coarse andthe fine resolution channels may be designed to function independently.

[0072] A challenging aspect of this design is to construct differentcoil-washer combinations to obtain proper transformer turns ratios, onthe same chip. By way of example, a challenging part of the design is tomake a washer and a coil of the same value, L₃, in the fine resolutionchannel. As shown in FIGS. 3 and 7-9, the L₃ washer is coupled to alarge coil L₂, while the L₃ coil is coupled to a small SQUID inductorL_(SQ). In one embodiment the values of inductance were selected to be400 pH, 1 μH, 1 nH, and 20 pH for L₁, L₂, L₃, and L_(SQ) respectively,where L_(SQ) is the inductance of SQ2. These values may be changed toaccommodate different design requirements. For example, in oneembodiment, since the coil-washer designs are very time consuming, theinductance values were chosen such that the same transformer designcould be used for both coarse and fine channels. In a particularembodiment the value of both L₁ and L₃ were chosen to be 500 pH. Thevalues of L₂ and L_(SQ) were kept at 1 μH and 20 pH respectively.Further details of the coarse and fine current resolution channels arediscussed below.

[0073]FIG. 4 is a simplified schematic of the coarse resolution digitalSQUID. The coarse resolution channel has an input inductor L1 (shown inFIG. 4 to have a value of 500 pH) coupled to SQUID SQ1. The output ofSQ1 is coupled through a step-down transformer T102 to comparator 101.In response to an externally applied clock identified as Clock A in FIG.3, the comparator 101 feeds back flux quantum, ±Φ₀, through the writegates (write gate 1 or 2 in FIG. 4) into the input coil, L1. Inpractice, this feedback loop (a superconducting path) is completed withan external pick-up loop, 10 a. In a test set up the pick-up loop wasreplaced with a step up transformer—a 20 pH washer coupled to a 500 pHcoil. The design of this transformer may be identical to the input coilL1 coupled to SQ1. The electrical schematic and layout of the FIG. 4circuit are shown in FIG. 5 and FIG. 6, respectively. In FIG. 5, theunits of junction critical currents, resistances, and inductances are inmA, ohms, and pH unless indicated otherwise.

[0074] The output from SQ1 is coupled to comparator, 101 by coupling atransformer T102 to a large inductance L11 (500 pH) and by coupling L11to a small (3.5 pH) comparator inductance L12. This was done byconstructing the large inductance (L11) from 8 smaller coils, as shownin FIG. 4, connected in series as detailed in FIG. 6. Each of these 8series inductors is coupled to one of 8 washers, which are connected inparallel.

[0075]FIG. 6 is a layout of the coarse resolution channel of the digitalSQUID. There are three levels of niobium (Nb) metal (M1, M2, and M3 ofthe standard HYPRES Corporation fabrication process whose specificationsare incorporated herein by reference). The Nb ground plane (M0 layer) ispresent everywhere except in specified areas. The ground plane holesenhance coupling in transformers.

[0076]FIG. 7 is a simplified schematic of the fine resolution digitalSQUID. The fine resolution channel has an input inductor (L₂=1 μH)coupled to the input of SQUID, SQ2, through a coupling/feedback stepdown transformer (L2-L3). The coupling/feedback step down transformerconsists of a 500-pH washer, coupled to L₂ and a 500-pH coil, coupled tothe SQUID, SQ2. The output of SQUID, SQ2, is coupled to comparator 102via a step down transformer T102 b. The comparator 102 feeds back ±Φ₀through write gates 1 and 2 into the feedback transformer (L3). The restof the fine resolution circuit is similar to the coarse resolutionchannel circuitry. In one embodiment, the current resolution of the finechannel was ΔI_(fine)=Φ₀/L₂=2 nA.

[0077] In FIGS. 7 and 8, the units of junction critical currents,resistances, and inductances are in mA, Ω, and pH, unless indicatedotherwise.

[0078] In the circuits shown in FIGS. 3, 4-6 and 7-9, a single clock(the input clock 100, clock A, clock B) may be used for the comparatorand the write gates. So operated the circuits exhibit extremely widedynamic range and reasonably low noise. This is an improvement over anearlier version that used two separate clocks for the comparator and thewrite gates. However, either a single clock or a two- phase clock may beused to practice the invention. Although the comparator shown in thefigures has a particular form, other suitable comparators may be used.

[0079]FIG. 3A shows “coarse” and “fine” current resolution channelssimilar to the ones shown in FIG. 3. However, the circuit of FIG. 3Aincludes additional controls applied via a clock controller 300 tocomparators 101 a, 102 a. One set of controls are used to control theapplication of the clocks to the comparators already noted above and asfurther discussed below. Furthermore, the clock controller 300 includescircuitry controlling the application of a clock signal (clock A1, B1,A2 or B2) to the comparators. In one mode of operation, the clockcontroller senses the presence of signals (e.g., pulses) at the outputsDO1 a, DO2 a, of the comparators and supplies clock signals forcontrolling the sampling by the comparators.

[0080] Another set of control signals includes threshold settings 1 and2 which are used to bias the threshold (flux bias) levels of comparators102 a, 102 a. The flux bias may be used to set the switching of therespective comparators either around a zero threshold or a non-zerothreshold. The comparators include write gates (e.g., see FIG. 4A) withindependent biases (e.g., current biases I11 and 12). The independentwrite gate biases control the threshold levels for the production ofpulses at the outputs DO1 a, DO2 a of the comparators, which pulses areused for output and feedback.

[0081] Referring to FIG. 4A, which is a more detailed view of acomparator useable in circuits embodying the invention, note that thecurrent biases (I1, I2) of the two write gates (WG1 and WG2) of acomparator, control the injection of fluxons into the input loop ineither direction. Instead of using a common bias that makes the twothresholds equal, by changing these biases independently, the two(higher and lower) thresholds can be controlled independently. The fluxbias introduces an additional constant flux in the loop which sets thethreshold for switching J2 or J3 when the clock pulse is applied. Ifflux bias is zero, J2 and J3 switch when the input flux is greater thanor less than zero. Otherwise, they switch when the input flux is greaterthan or less than the added bias flux.

[0082] Using different bias level for setting different thresholdlevels, a comparator circuit of the type shown in FIG. 4A, in responseto a clock pulse, produces either

[0083] (1) a feedback of −Φ₀, by switching “write gate 2” and a 2-bitbinary output (01 or 10) if the input flux coupled from the DC SQUID isless than a lower threshold Φ_(L)).

[0084] (2) a feedback of +Φ₀, by switching “write gate 1” andcomplementary binary outputs (10 or 01) if the input flux is more than ahigher threshold (Φ_(H)).

[0085] (3) no feedback is produced if the applied flux is Φ_(L)<Φ<Φ_(H)and no output is produced (0 0).

[0086] The comparator output of FIG. 4A may have three possible values.Assigning binary values to the outputs on lines X and Y, the binaryoutput may be 01, 10 or 00. This 2-bit digital code may be converted toa differential code (‘01’=−1, ‘00’=0, ‘10’=+1) by a gate and applied toa bi-directional (up-down) counter.

[0087] Often the threshold levels are chosen to be symmetric around 0(Φ_(L)=−Φ_(H)) and sometimes are both equal to zero. In the case wherethe two thresholds are equal, Φ_(L)=Φ_(H), the comparator output canthen only be one of two values and can be described as a circuit that inresponse to a clock pulse produces either

[0088] (1) a feedback of −Φ₀, by switching “write gate 2” and binaryoutput (1 or 0) if the input flux is less than a threshold

[0089] (2) a feedback of +Φ₀, by switching “write gate 1 ” andcomplementary binary output (0 or 1) if the input flux is more than athreshold.

Clocking Scheme

[0090] For optimum operation, a controlled clocking scheme of amulti-channel subranging digital SQUID based ADC is desirable. First ofall, the clocks for each channel may be derived from a common masterclock. For example, a two-channel device may be clocked using alternateclock phases generated from a two-phase clock source. In addition, aclock controller (e.g., 300 in FIG. 3A) may be used to apply a set ofone or more clock pulses to each channel following an algorithm toensure correct operation.

[0091] For example, assume a two-channel device with a coarse channelwith signal resolution LSB_(coarse) and a fine channel with signalresolution LSB_(fine), where LSB is the least significant bit or thesmallest signal that can be resolved. The comparator (e.g., 101, 102,101 a, 102 a) is a circuit that in response to a clock pulse produceseither

[0092] (1) a feedback of −Φ₀, by switching “write gate 2” and binaryoutputs (1, 0) if the input flux is less than a lower threshold (Φ_(L))

[0093] (2) a feedback of +Φ₀, by switching “write gate 1 ” andcomplementary binary outputs (0, 1) if the input flux is more than ahigher threshold (Φ_(H)).

[0094] (3) no feedback is produced if the applied flux is Φ_(L)<Φ<Φ_(H)and no output is produced (0, 0).

[0095] These outputs may be generated in complementary fashion and arein the form of SFQ pulses. Often the threshold levels are chosen to besymmetric around 0 (Φ_(L)=−Φ_(H)) and sometimes are both equal to zero.One clock controlling algorithm is as follows:

[0096] Step 1: Set the thresholds of the coarse and the fine channelcomparators

[0097] Step 2: Apply a set of consecutive clock pulses to the coarsecomparator until the applied flux is between the two thresholds and doesnot produce any feedback.

[0098] Step 3: Apply a set of consecutive clock pulses to the finecomparator until the applied flux is between the two thresholds and doesnot produce any feedback.

[0099] Step 4: Repeat Steps 2 and 3.

[0100] Definition of Sensitivity and Resolution: Sensitivity of ameasuring device is the smallest signal that can be detected in thepresence of noise. SQUIDs are very sensitive measurement devices formagnetic flux. Resolution is a property of a digital device and refersto the smallest discrete level. This is also referred to as the leastsignificant bit (LSB). The fundamental flux resolution of a SQUID-baseddevice is a single flux quantum (F0), but the resolution of an ADC canbe improved further through digital filtering if the sampling frequencyis higher than the twice the signal bandwidth (Table 1).

[0101] An example of one mode of operation of the circuit of FIG. 3, orFIG. 3A, when coupled to processing circuitry 130 of the type shown inFIG. 13 is discussed below. In this example, all quantities arerepresented as decimal numbers. Assume that a signal of 34.3 units isapplied instantaneously to the circuit of FIG. 3 or FIG. 3A. Assume thatthe resolution of the coarse channel is 10 units and that of the finechannel is 1. The following clocking algorithm may be used:

[0102] 1) Set the “coarse” channel comparator thresholds at +9 and −9,and set the “fine” channel comparator threshold at 0.

[0103] 2) Apply clock pulses to the “coarse” channel until itscomparator (101, 101 a) produces a zero output (when the signal isbetween the upper threshold of +9 and the lower threshold of −9).

[0104] 3) Then, apply clock pulses to the “fine” channel until itscomparator (102, 102 a) output changes sign.

[0105] 4) Repeat steps 2 and 3.

[0106] For the assumptions noted above, the sequence of clock events andclock cycles to which the circuit is placed is summarized in Table 2,below. Note that “Events” 10-12 will repeat indefinitely until thesignal value is changed. The average accumulated output is between 34and 35, implying that the error is less than the least significant bitof 1 in the fine channel.

[0107] The situation is a little more complicated for the measurement oftime varying input signals. Especially for fast changing signals, wheremost of the tracking has to be performed by the coarse channel, theclocking algorithm may have to be changed to allow for the thresholdsand the clocking sequence of the coarse and the fine channels toalternate. FIGS. 5 10 and 11 show an example of the output signals fortwo different threshold criteria for the coarse channel (±7 in Output−1and ±2 in Output−2) for a linearly increasing input signal. The timeunit is the clock period. TABLE 2 Signal remaining in SQUID AccumulatedEvent Clock applied to the input loop Output Output (Count) 1 Coarsecomparator 34.3 10  10 2 Coarse comparator 24.3 10  20 3 Coarsecomparator 14.3 10  30 4 Coarse comparator 4.3 0 30 5 Fine comparator4.3 1 31 6 Fine comparator 3.3 1 32 7 Fine comparator 2.3 1 33 8 Finecomparator 1.3 1 34 9 Fine comparator 0.3 1 35 10  Fine comparator −0.7−1   34 11  Coarse comparator 0.3 0 34 12  Fine comparator −0.3 1 35 13 Fine comparator −0.7 −1   34 14  Coarse comparator 0.3 0 34 15  Finecomparator −0.3 1 35

[0108]FIG. 12 is a block diagram of a system employing the SQUIDtechnology in accordance with the invention. The output of a pick-upcoil 10 (or 10 a) is coupled to a digital SQUID chip 20, of the typedescribed in FIGS. 3-9 or in FIGS. 18 and 19, described below. Theoutputs of chip 20 are supplied to digital filter circuitry 130 whoseoutputs may be further processed by a data acquisition and analysissoftware processor 138. The resolution of the digital SQUID 20 isquantized. The raw flux and current resolutions are Φ₀ (2.07 fWb) andΦ₀/L, where L is the input inductance. The foregoing statement appliesfor a single channel digital SQUID; for a subranging digital SQUID, itapplies to the channel with the highest resolution. For a 1 μH inputinductance, the current resolution is about 2 nA. However, for slowlyvarying or dc signals the resolution can be increased by over sampling.If the clock frequency is higher than the Nyquist rate for a givensignal bandwidth, the resolution can be improved further by averagingthe digital SQUID output. A digital filter can be employed to performthis averaging. The resolution improves by a factor of {squareroot}{square root over (α)}, where α is the over sampling ratio (OSR).If the input bandwidth is 100 Hz and the clock frequency is 200 MHz, theresolution can be improved by a factor of 1000 to 2 pA. On the otherhand, if the input bandwidth is 1 MHz, the current resolution can beimproved only by a factor of 10 to 200 pA.

[0109] One of the main advantages of the digital SQUID approach is thesimplicity of the peripheral electronics, which can be easily extendedfor multiple channels, i.e., more than just one coarse and one finechannel may be used in the subranging scheme to process the input signalfrom the pick up coil. The peripheral electronics may include a digitalintegrator (decimation filter) and signal processing software. Thedigital integrator can be a counter/accumulator circuit implemented inprogrammable logic as shown in FIG. 13.

[0110]FIG. 13 includes a block diagram of circuitry for processing theoutputs DO1 and DO2 shown in FIG. 3 (or DO1 a, DO2 a shown in FIG. 3A)where each digital SQUID output is a 1-bit (or a 2-bit) delta code. Thiscode is converted via gates 131 a, 131 b into a differential code andapplied to an up-down counter 132 a, 132 b. The counts are accumulatedover the read cycle in an accumulator 136 a, 136 b. A read clock isobtained by dividing the clock frequency by 2^(n) in a frequency divider134 a, 134 b. The outputs of the accumulators 136 a, 136 b represent theaverage reconstruction of the input signal applied to the digitalSQUIDs.

[0111] The principle of operation of the digital SQUID circuit has beendescribed using a 1-bit and a 2-bit delta modulator. The output of thedigital SQUID comparator (101, 102) is a “1-bit delta code”. The outputsof the digital SQUID comparators (101 a, 102 a) may be a “1-bit deltacode” or a 2-bit delta code, as described above. In each clock cycle,the comparator produces a signal which may be defined as a binary “1”(e.g., when the DC SQUID senses positive flux) or a signal which may bedefined as a binary “0” (e.g., when the DC SQUID senses negative flux)as its digital output. A gate (e.g., 131 a, 131 b), with differentialoutput, is used to convert this digital output into a differential codeat the input of the up-down counter (132 a, 132 b). When the digitalSQUID output is “1” (“0”) the gate sends a signal from its positive(negative) output to the “up” (“down”) input of the counter. However, asnoted above for FIGS. 3A and 4A by setting different threshold levels a2-bit delta code may be outputted from each comparator.

[0112] Each one of up-down counters 132 a, 132 b is non-destructive andshould be large enough for the dynamic range of interest. The countersends the raw reconstructed output to an accumulator 136 a, 136 b thatis read out periodically, in response to a read clock signal. This readclock may be derived by decimating the clock by an n-bit binaryfrequency divider 134 a, 134 b. The counter/accumulator combination actsas a digital low-pass filter. A version of this digital filter was builtusing room-temperature field-programmable gate arrays (FPGA) with a28-bit counter and a decimation ratio of 2¹⁴ for a clock frequency (f)of 15 MHz. A very high frequency (20-25 GHz) version of this filter wasalso developed using superconducting RSFQ electronics to build ahigh-resolution analog-to-digital converter (FIG. 14). However, thesuperconducting versions include complex digital circuits (severalthousand JJs) and suffer from low fabrication yield. Therefore, a roomtemperature version may be better suited for low speed (up to 20 MHz)applications. However, either scheme may be used.

[0113]FIG. 14 is a micro-photograph of a high resolutionanalog-to-digital circuit suitable for use with digital SQUIDs embodyingthe invention; capable of producing 96 dB spur-free dynamic range (SFDR)and 14-bit signal-to-noise ratio (SNR) at 10 MSample/s. It runs with aninternal 20 GHz clock and a programmable clock frequency divider. Thedecimation filter has been operated up to 25 GHz clock frequency. Thisfast, pipelined filter is a complex RFSQ circuit with more than 3000Josephson junctions. A similar digital filter can be used to increasethe digital SQUID performance of the circuitry 130 shown in FIG. 13.

[0114] The output of the peripheral electronics is serialized and may beconnected to the serial port of a computer (e.g., processor 138) forsignal processing.

[0115] Another consideration for measurement systems where the digitalSQUID device will be used, such as in accelerator beam currentmeasurement systems, is the stray magnetic field in the acceleratorenvironment. The shielding requirements for a digital SQUID is much lesssevere than that for an analog SQUID, due to its unlimited dynamicrange. Any dc magnetic field can be compensated for through feedback.Even slowly varying magnetic fields can be tracked and subtracted out bythe digital SQUID. However, transient fields will be measured by thedigital SQUID as additional noise. We can use a superconducting (Nb)shield in addition to the standard mu-metal shields to provide betterimmunity from time-varying stray magnetic fields. Also, the pick-up coilcan be designed so as to cancel orthogonal components of magnetic field.Finally, the room-temperature digital filter is a programmable low-passfilter. High frequency noise due to rf magnetic fields will be filteredout by limiting the measurement bandwidth to that of thesignal-of-interest (SOI). Since this measurement bandwidth isprogrammable, it can be altered to maximize the signal to noise ratio ofthe digital SQUID ammeter.

[0116] As noted, systems embodying the invention may includesuperconducting circuitry for the subranging digital SQUID, peripheralelectronics and data analysis software development and systemintegration.

[0117] The subranging architecture combines a coarse and a fineresolution channel by placing an input coil L1 (e.g., 500-pH) for thecoarse channel in series with an input coil L2 (e.g., 1 μH) for the finechannel. An important aspect of the invention is the layout of the twochannels on the same chip. A possible layout of L1, L2 and L3 is shownin FIG. 15.

[0118]FIG. 16 shows a two-clock comparator which may be used in circuitsembodying the invention. However, a comparator with a single-phase clockmay be used to clock each one of the “coarse” and “fine” channelcomparators as shown in FIGS. 3, 4, 5, 7 and 8.

[0119] The output digital signal level from the digital SQUID (D-SQUID)chip is about 1 mV. The peripheral electronics may include any suitablepre-amplifiers (100×) and digital filters. The electronics unit includesa computer interface and may include a computer such as processor 138[shown in FIGS. 12 and 13.]

[0120] The data analysis for the subranging device is more complicatedthan that of a single channel device. The data from the coarse and thefine resolution channels must be combined in software and/or viahardware (e.g., processor 138) to produce the complete dynamic range ofthe signal. One option is to design the channels so that their rangesare non-overlapping, as shown in FIG. 17(a). For this option, the totalrange is the sum of the two ranges and the two digital numbers from thecoarse and fine resolution channels can be concatenated. The otheroption is to have a slight overlap between the two ranges, as shown inFIG. 17(b), so that the most significant bit(s) (MSB) of the finechannel can be compared to the least significant bit(s) (LSB) of thecoarse channel. The second option allows digital error-correctionalgorithms to be implemented.

[0121]FIG. 18 shows how two or more such ADCs can be combined in thesubranging architecture through an arrangement of superconductingtransformers and delay lines.

[0122] An input signal from a pick-up coil is applied to an inductor L1(for the coarse conversion) and, in parallel thereto, analog delaynetwork 181 in series with an inductor L2 (for the fine conversion). L1is coupled to a “coarse” SQUID based ADC 183. The output of ADC 183 iscoupled to a digital filter 185 and to the input of a digital variabledelay line 187. The output of delay line 187 is supplied to adigital-to-analog converter (DAC) 189 whose output is supplied to aninductor L190 which is part of a subtracting network 191. The “coarse”signal produced across L190 is subtracted from the delayed analog inputsignal across L2. The result of the subtraction is coupled via L192 tothe input of a “fine” SQUID band ADC 193. The output of ADC 193 issupplied to the input of a digital filter 195. The outputs of digitalfilters 185 and 195 are supplied to a processor 198 which functions toreconstruct the signal via the hardware in the processor and itsprogramming. As noted above, there may be more channels than just the“coarse” and “fine” channels shown in FIG. 18.

[0123] The feedback path (including delay network 187, DAC 189 andinductor L190) must include a digital-to-analog converter (DAC) withappropriate delay. In the simple 1-bit delta modulator, a DAC is notrequired. But for multi-bit code generated by a more complex ADC (e.g.,183), a multi-bit DAC is necessary to reproduce the analog signal to besubtracted from the input analog signal. This subtraction can be done byan arrangement of multiple coupled inductors, as shown in FIGS. 18 and19. This subtractor circuit includes a superconducting transformer withvery high linearity. Therefore, the linearity of the analog signalsubtraction process will not deteriorate the highly linearsuperconducting ADC front-end. High-linearity in analog-to-digitalconversion produces high spurious free dynamic range (SFDR), animportant performance metric for ADCs.

[0124] The same input signal is applied to the coarse and the fine ADC.There is a fixed (analog) time delay (due to network 181) in the signalpath to the fine ADC 193 to compensate for the processing time of thecoarse ADC front-end 183 and the DAC 189. An adjustable digital delay187(which may be a Josephson transmission line) is introduced betweenthe outptut of ADC 183 and the DAC 189, while the signal is in thedigital domain. The adjustable digital delay 187 is introduced toexactly match the timing of the input signal to inductor L2 and the DACoutput to inductor L190 so the subtractor 191 works on the correctportion of the signal.

[0125]FIG. 18 shows an arrangement where a total dynamic range of 25bits (or 2²⁵ or 33 million) is divided into two ranges. However, itshould be understood that the subranging architecture could have beenextended to more than two ranges. However, most applications can becovered by two to three sub ranges.

[0126] Note: FIGS. 18 and 19 are directed to the more general case of“superconducting subranging analog-to-digital converter”. Theimplementation with simple 1-bit delta modulator ADC shown in FIGS. 3,4-6, 7-9 and 13 and the 2-bit delta in FIGS. 3A and 4A help explain theconcept but may be viewed as a subset of the general case illustrated inFIGS. 18 and 19.

[0127] Note: A digital SQUID is essentially a euphemism for asuperconducting ADC. The analog SQUIDs were originally applied forprecision measurement of magnetic fields, currents, etc . . . The simpledigital version, with digital feedback is called a digital SQUID; butfunctionally it is an analog-to-digital converter. This is described, inpart, in U.S. Pat. No. 5,420,586 titled Superconducting Analog ToDigital Converter Type Circuit issued to M. Radparvar and assigned toHypres Inc., and the teachings of which are incorporated herein byreference.

[0128] The invention may be incorporated in a versatile precisioninstrument that can be used in a wide variety of measurements in nuclearaccelerator beam diagnostics, as well as in other fields. The instrumentfunctions as a precision high-resolution digital ammeter with anextremely large dynamic range by utilizing a digital SQUID technique.

[0129] Superconducting electronics have several intrinsic advantagesthat are exploited by the proposed digital SQUID current measurementinstrument.

[0130] Quantum Accuracy—The device accuracy is defined by magnetic fluxquanta set by a ratio fundamental physical constants Φ₀=h/2e).Therefore, it is a single fluxon device and can provide quantummechanical accuracy.

[0131] Low Noise—Cryogenic (4 Kelvin) operation ensures reduced thermalnoise (75 times smaller than room temperature).

[0132] Radiation Hardness—The all-thin-film fabrication technology usedfor superconducting electronics is intrinsically radiation hard.

[0133] Simple Low-cost Fabrication—Implemented in an all thin filmprocess, both the development and fabrication cost per wafer isconsiderably lower than other semiconductor technologies.

[0134] Ultra-high Speed—Even with a 3-μm fabrication process, complexcircuits have been demonstrated, including basic logic gates at 100 GHzand analog-to-digital converters at 20 GHz sampling rates. Gate speedincreases with reduction in junction size. Sub-micron logic gates(toggle flip-flops) in the RSFQ technology have even been experimentallydemonstrated to operate at >750 GHz—no other technology has even beensimulated at this speed.

[0135] In applications which do not require measurement of highfrequency signals, low-speed room-temperature electronics may be used toperform the necessary digital signal processing. However, thistechnology can be extended to rf applications, where the signalbandwidth is in the 10 MHz to 10 GHz range, by implementing the digitalsignal processing hardware in superconducting electronics.

[0136] On-chip signal processing circuitry with rapid single fluxquantum (RSFQ) logic may be used with this technology.

[0137] Digital SQUID technology presents the opportunity to realize aprecision current measuring instrument with the following set ofattractive features

[0138] Extremely large dynamic range—Theoretically unlimited,practically limited by the current carrying capacity of superconductingwires

[0139] High resolution—Raw resolution of 1-2 nA, can be improved to afew pA by over-sampling when the signal bandwidth is small.

[0140] Fast slew rate—Slew rate is proportional to the clock frequency.

[0141] High sensitivity—Sensitivity, determined by the analog SQUIDfront-end, is ˜10⁻⁶Φ₀/{square root}Hz

[0142] Programmable measurement bandwidth—By changing the read clockfrequency using a programmable decimation counter, the measurementbandwidth can be changed.

[0143] Simple and inexpensive room temperature electronics—Roomtemperature electronics is digital and can be implemented inprogrammable logic. It is easily extendible to a multi-channel system.

[0144] Utilizing a digital SQUID technique in accordance with theinvention a precision high-resolution digital ammeter may be formed withan extremely large dynamic range. This type of product will result in aversatile, precision instrument that can be used in a wide variety ofmeasurements in nuclear accelerator beam diagnostics, as well as inother fields. First, we give examples of applications of this instrumentfor beam diagnostics.

[0145] 1) A BCM (beam current monitor) measures the total circulatingcharge in an accelerator and measures any variation over time. Since BCMmeasures average beam current, it is low bandwidth signal (almost dc).For true dc measurement, a superconducting pick-up coil must be used.This integrates well with a cryogenic superconducting measurementdevice, a SQUID. The challenge in this measurement is to achieve a veryhigh resolution (at least 10⁻⁶) as well as a very large dynamic range.The digital SQUID ammeter is ideal for this application. Since the slewrate of the signal to be measured is low, the digital SQUID will be ableto track the signal with almost unlimited dynamic range. The onlylimitation on the dynamic range arises from the current carryingcapacity of the superconducting pick up coil. However, the currentlevels in most accelerators range from 100 μA to 100 mA which is wellbelow the current carrying capacity of superconducting wires.

[0146]  In accordance with the invention, a BCM with a raw resolution of2 nA resolution may be produced. BCM measures average beam current.Therefore, it is low bandwidth signal (almost dc). The resolution willbe further improved, by as much as 3 orders of magnitude to 2 pA, byaveraging using a room-temperature decimation filter. The large dynamicrange will allow measurement of average circulating beam currents in therange of mA with resolution of 10⁻⁶-10⁻⁹.

[0147] 2) By implementing a novel subranging architecture, involvingalternate clocking of a coarse resolution and a fine resolution digitalSQUID, in accordance with the invention, a beam-in-gap (BIG) monitor maybe made.

[0148]  The BIG monitor needs to measure a few mA gap currents with aresolution of at least 100 μA. At the same time, it must measure thebunch current which is as large as 100 A.

[0149] Therefore, the required dynamic range can be as high as 10⁶ (20bits). This task is made even more challenging by the fact that thesignal bandwidth is in the MHz range. A single digital SQUID would notbe able to track the signal over the large dynamic range since thesignal slew rate is large. This problem is resolved in accordance withthe invention, by subdividing the total dynamic range into two smallerranges and using two digital SQUIDs. The first (coarse) device measuresthe signal in larger steps leaving a residual signal that is less thanits step size. The second (“fine”) device resolves this residual signalin smaller steps, providing the required fine resolution. The coarse andthe fine resolution can be adjusted by designing appropriatetransformers.

[0150] 3) Direct measurement of beam polarization may also be possibleby improving the resolution to <10⁻⁸. However, since this must be donewith kHz bandwidths, a very high frequency clock (>10 GHz) may berequired along with on-chip digital filtering using RSFQ (rapid singleflux quantum) logic. This may be achieved by integrating high-speedon-chip clocks and filters with the digital SQUID device.

[0151]  Note: A three-range device may be necessary to cover the 27 bitdynamic range, required for this application. The proposed sub-rangingtechnique embodying the invention is extendible to additional channels(i.e., more than just a single coarse and fine channel may be used incircuits and systems embodying the invention to process the inputsignal).

[0152] The invention is not restricted to measurement of current. Theinvention may be used to make a high precision magnetometer orvoltmeter. SQUID magnetometers are widely used for non-destructiveevaluation and non-invasive biomagnetic measurements. Significant costreduction in such systems may be facilitated by the use of a digitalSQUID instead of the analog SQUID that is currently used. The roomtemperature electronics is much simpler in the case of digital SQUID andthe large dynamic range obviates the need for expensive shielded roomsthat are needed by present SQUID magnetometer systems.

[0153] Commercial SQUID magnetometers are widely used as biomagneticsensors to measure weak magnetic fields in heart muscle(magnetocardiogram), in the brain (magneto-encephalogram), and inskeletal muscle (magnetomyogram). Existing SQUID systems useconventional RF and DC SQUIDs with room-temperature electronics. Thefield imposed on the SQUID is transformed to a voltage by the SQUID andis sensed by an electronic circuit. SQUID magnetometer systems developedfor biomedical applications use shielded rooms with walls several inchesthick. The major single-item cost of most SQUID-based biomedical systemsis associated with this elaborate magnetic shielding. The digital SQUIDsystem embodying the invention, because of its large dynamic range, iscapable of discriminating weak signals against large non-varying ambientfields and will not require elaborate shielding. Thus the cost of suchsystems can be significantly reduced by using the digital SQUIDapproach.

[0154] There are several military applications, such as electronicwarfare (EW) and signal intelligence (SIGINT) systems, where very largedynamic range and resolution are required.

[0155] In SIGINT systems, the signal of interest must be discriminatedfrom other interfering signals and noise. For this application, adynamic range of 20-25 bits (120-150 dB) is required over a bandwidth of5-10 MHz. This task is similar to the BIG monitor, except that both thelarge and small signals of interest occur at the same time. Thesubranging digital SQUID technology is suitable for these SIGINTsystems. To achieve better resolution over larger bandwidth, amulti-comparator ADC and a digital-to-analog converter (DAC) may be usedbefore the signal is fed back to the input. High-resolution ADC andultra-linear DAC circuits utilizing the quantum accuracy feature of thesuperconducting electronics manufactured by the assignee of the presentinvention may be used to practice and/or in conjunction with the presentinvention. These can be incorporated into the subranging architecture toachieve higher performance digital SQUIDs. The development of suchsystems will enable the realization of higher performance devices.

[0156] In EW systems, the problem is detection of unintentionalmodulation of pulsed radars. This application demands even higherbandwidth (25-100 MHz) with >100 dB dynamic range and 96 dBsignal-to-noise ratio (SNR), equivalent to about 16 bits of resolution.Again, a high-performance subranging digital SQUID is well suited forthis application. Fast RSFQ on-chip signal processing circuits may beused to provide higher performance.

[0157] The subranging architecture can be implemented using any numberof suitable analog-to-digital converters (ADCs). The description in FIG.3 was for a single-comparator ADC or a 1-bit delta modulator. Increasedslew rate (more bits at higher bandwidth) may be obtained by using morecomplex ADCs with on-chip fast digital filters (as an example, see FIG.14 which is a micro-photograph of the high resolution analog-to-digitalcircuit). A high resolution ADC may also be of the type shown in anarticle titled “Progress in the Development of a SuperconductiveHigh-Resolution ADC”, by Mukhanov, Brock, Kirichenko, Rylov and Vogtpublished in Extended Abstracts 1999 Intl. Supercond. Elec. Conf.(ISEC'99).

What is claimed is:
 1. A subranging superconducting analog-to-digitalconverter (ADC) comprising: means for applying an analog input signal toan input coil having at least a first inductive section and a secondinductive section; a first superconducting quantum interference device(SQUID), coupled to said first inductive section, responsive to saidanalog input signal for producing a first output signal; a firstcomparator responsive to said first output signal of the first SQUID andto a first clock signal for producing a first output signal which iscoupled back to said input coil; a second superconducting quantuminterference device (SQUID), coupled to said second inductive section,responsive to said analog input signal for producing a second outputsignal; and a second comparator responsive to said second output signalof the second SQUID and to a second clock signal for producing a secondoutput signal which is coupled back to said input coil.
 2. Thesubranging superconducting ADC as claimed in claim 1, wherein said firstand second clock signals are applied to said first and secondcomparators for enabling one of them at a time.
 3. The subrangingsuperconducting ADC as claimed in claim 1, wherein the inductance of thesecond inductive section is greater than the inductance of the firstinductive section; wherein the first SQUID and the first comparator aredesigned to produce a coarse, low resolution, output; and wherein thesecond SQUID and the second comparator are designed to produce a fine,high resolution, output.
 4. The subranging superconducting ADC asclaimed in claim 3, wherein each one of said first and secondcomparators is a superconducting comparator; with each one of said firstand second comparators being responsive to an output signal of itscorresponding SQUID and to a clock signal for producing a first outputsignal having a first value and a second output signal having a secondvalue, complementary to said first value; the first output signal beingcoupled to a first write gate and the second output signal being coupledto a second write gate; the first write gate producing a comparatoroutput signal of one value and the second write gate producing acomparator output signal of complementary value; and wherein the twooutput signals of the first and second comparators are coupled back tothe input coil.
 5. The subranging superconducting ADC as claimed inclaim 4, wherein each one of said first and second SQUIDs has an outputfor respectively producing said first and second output signals; andwherein each output includes an output coil for inductively coupling theoutput signals of each SQUID to an input of its correspondingcomparator.
 6. The subranging superconducting ADC as claimed in claim 5,wherein the second inductive section of the input coil is coupled to aninput of the second SQUID via an isolation transformer.
 7. Thesubranging superconducting ADC as claimed in claim 5, wherein each oneof said first and second comparators produces a digital output, with thedigital output of the first comparator defining the more significantbits and the digital output of the second comparator defining the lessersignificant bits of the digitally converted signal.
 8. The subrangingsuperconducting ADC as claimed in claim 7, wherein the digital output ofeach comparator is coupled to an up-down counter, each up-down counterhaving an output coupled to an accumulator whose output is coupled to aprocessor for combining the outputs derived from the first and secondcomparators.
 9. The subranging superconducting ADC as claimed in claim8, wherein the accumulator is responsive to a clock signal derived froma master clock and the first and second clock signals are derived fromthe same master clock.
 10. The subranging superconducting ADC as claimedin claim 7, wherein the digital output of each comparator is a 1-bitdelta code.
 11. The subranging superconducting ADC as claimed in claim10, wherein the 1-bit delta code output from each comparator is appliedto a gate circuit for converting each 1-bit delta code output into adifferential code applied to an up-down counter.
 12. The subrangingsuperconducting ADC as claimed in claim 1, wherein each one of saidfirst and second SQUIDs is an analog SQUID.
 13. The subrangingsuperconducting ADC as claimed in claim 1, wherein the first and secondinductive sections are connected in series and wherein the inductance ofthe second inductive section is greater than the inductance of the firstinductive section.
 14. The subranging superconducting ADC as claimed inclaim 1, wherein the first comparator produces a first quantized outputsignal and the second comparator produces a second quantized outputsignal.
 15. The subranging superconducting ADC as claimed in claim 3,wherein each one of said first and second comparators is asuperconducting comparator; with each one of said first and secondcomparators being responsive to an output signal of its correspondingSQUID and to a clock signal for producing a first output signal having afirst value and a second output signal having a second value,complementary to said first value; the first output signal being coupledto a first write gate and the second output signal being coupled to asecond write gate; the first write gate being settable to a firstthreshold level and the second write gate being settable to a secondthreshold level for enabling the first and second write gates to producean output signal having: (a) a first value when the input signal to thecomparator is greater than the first threshold level, (b) a second valuewhen the input signal is below the second threshold level, and (c) athird value when the input signal is between the first and secondthreshold levels; and wherein the output signals of the first and secondcomparators are coupled back to the input coil.
 16. The subrangingsuperconducting ADC as claimed in claim 15, wherein each write gateincludes a SQUID with means for selectively applying a different biascurrent to each write gate SQUID.
 17. A subranging superconductinganalog to digital converter (ADC) comprising: means for applying aninput signal to an input coil having at least a first inductive sectionin series with a second inductive section; a first superconductingquantum interference device (SQUID) coupled to said first inductivesection responsive to an input signal for producing a first outputsignal; a first comparator responsive to said first output signal of thefirst SQUID for producing a quantized signal of a polarity to subtract afirst fixed amount from the input signal; a second superconductingquantum interference device (SQUID) coupled to said second inductivesection responsive to an input signal for producing a second outputsignal; a second comparator responsive to said second output signal ofthe second SQUID for producing a quantized signal of a polarity tosubtract a second fixed amount from the input signal.
 18. A subrangingsuperconducting ADC as claimed in claim 17, wherein a clock signal isapplied to said first and second comparators for enabling one of them ata time.
 19. A subranging superconducting ADC as claimed in claim 18,wherein: (a) the first comparator has an input connected to said outputof said first SQUID and has a first coarse output coupled to said inputcoil and a second coarse output at which is produced a first digitalsignal; (b) the second SQUID is coupled via an isolation transformer tosaid second section of said input coil; and (c) the second comparatorhas an input coupled to said output of said second SQUID and has a firstfine output coupled to said isolation transformer and a second fineoutput at which is produced a second digital signal.
 20. A subrangingsuperconducting ADC as claimed in claim 19, wherein the outputs of thefirst and second comparators are processed and combined to produce afull digital representation of the analog input signal.
 21. A subrangingsuperconducting ADC as claimed in claim 18, wherein the inductance ofthe second inductor is greater than the inductance of the firstinductor.
 22. A subranging superconducting analog to digital converter(ADC) including: means for applying an analog input signal to an inputcoil having at least a first inductive section and a second inductivesection; a first superconducting quantum interference device (SQUID)having an input coupled to said first inductive section and having anoutput coupled to an input of a first comparator, said first comparatorhaving an output for producing a first signal when the analog inputsignal exceeds a first reference level and for producing a second signalwhen the analog input signal does not exceed said reference level; asecond superconducting quantum interference device (SQUID) having aninput coupled to said second inductive section and having an outputcoupled to an input of a second comparator, said second comparatorhaving an output for producing a third signal when the analog inputsignal exceeds a second reference level and for producing a fourthsignal when the input signal does not exceed said second referencesignal; and means coupling the outputs of the first and secondcomparators to the input coil.
 23. A subranging superconductinganalog-to-digital converter (ADC) comprising: input means for applyingan analog input signal to a first inductor; first means inductivelycoupling the first inductor to an input of a “coarse” SQUID based ADCfor producing at an output thereof a coarse, low resolution, outputsignal; means coupling an output of the “coarse” SQUID based ADC to afirst digital filter means coupling an output of the “coarse” SQUIDbased ADC via a digital variable delay line to a digital-to-analogconverter (DAC); means for coupling the analog input signal via ananalog delay network to a second inductor; means coupling an output ofthe DAC to a third inductor arranged to subtract the DAC output from theanalog input signal supplied to the second inductor; means couplingsignals resulting from the subtraction to an input of a “fine” SQUIDbased ADC for producing at an output thereof a fine, high resolution,output signal; means coupling an output of the “fine” SQUID based ADC toa second digital filter; and means coupling the outputs of the first andsecond digital filters to a processor for reconstructing the inputsignal.
 24. The subranging superconducting analog-to-digital converter(ADC) as claimed in claim 23, wherein the analog delay network delaysthe propagation of the input signal for a length of time which isapproximately equal to the time taken to process the input signalthrough the “coarse” SQUID based ADC, the digital variable delay networkand the DAC.
 25. The subranging superconducting analog-to-digitalconverter (ADC) as claimed in claim 23, wherein the digital variabledelay network may be controlled to ensure that the time taken to processthe input signal through the “coarse” SQUID based ADC and, the digitalvariable delay network and the DAC matches precisely the delay throughthe analog delay network.
 26. A subranging superconducting ADCcomprising: means supplying an analog input signal to first and secondcircuit networks; said first circuit network including a first inductorfor coupling the analog input signal to a first SQUID circuit forproducing “coarse” (high amplitude, low resolution) output signals inresponse to said analog input signal; a subtractor network forsubtracting from the analog input signal a signal corresponding to anoutput of the first SQUID and for supplying the resultant signal to aninput of a second SQUID circuit for producing “fine” (low amplitude,high resolution) output signals in response to said analog input signal;and neans coupling an output from each one of said first and secondSQUIDs to a digital filter.
 27. A subranging superconducting ADC asclaimed in claim 26, wherein, the circuitry for subtracting an output ofthe first SQUID based circuit from the analog input signal includes ananalog delay line for coupling the analog input signal to a secondinductor and a digital variable delay network having an input connectedto the output of the first SQUID based circuit and having an outputconnected to the input of a digital-to-analog converter (DAC) with theoutput of the DAC being connected to a third inductor and supplying asignal thereto tending to cause the output of the first SQUID basedcircuit to be subtracted from the analog input signal developed acrossthe second inductor.